1.
Advancements In Post-Silicon Debugging And Verification For System-On-Chip Architectures. Eur. J. Emerg. Eng. Math. [Internet]. 2025 Jan. 1 [cited 2026 Feb. 22];2(01):01-5. Available from: https://www.parthenonfrontiers.com/index.php/ejeemt/article/view/544